/**
 * Copyright (C) 2021 - 2031 O-Cubes Co., Ltd.
 */

/****************************************************************
 *  @file    dw_spi_hal.h
 *  @brief   Designware spi controller hal header file
 *  @version v1.0
 *  @date    03. Apr. 2023
 *  @author  liuchao
 ****************************************************************/

#ifndef __DW_SPI_HAL_H__
#define __DW_SPI_HAL_H__

#include "dw_spi_hal_cfg.h"

/* DW APB SPI bit definitions */

/**
 * DesignWare SPI hal ctrl0 macros,
 * include dfs, scph, scppl, tmod, etc
 */
#define DW_SPI_CTRLR0_SC_OFS                    (6)
#define DW_SPI_CTRLR0_SC_MASK                   (0xC0)
#define DW_SPI_CTRLR0_SCPH_HIGH                 (0x40)
#define DW_SPI_CTRLR0_SCPH_LOW                  (0)
#define DW_SPI_CTRLR0_SCPOL_HIGH                (0x80)
#define DW_SPI_CTRLR0_SCPOL_LOW                 (0)

#define DW_SPI_CTRLR0_TMOD_MASK                 (0x300)
#define DW_SPI_TMOD_TRANSMIT_RECEIVE            (0)
#define DW_SPI_TMOD_TRANSMIT_ONLY               (0x100)
#define DW_SPI_TMOD_RECEIVE_ONLY                (0x200)
#define DW_SPI_TMOD_EEPROM_READ_ONLY            (0x300)

#define DW_SPI_CTRLR0_FRF_MOTOROLA              (0x0)
#define DW_SPI_CTRLR0_FRF_TI                    (0x10)
#define DW_SPI_CTRLR0_FRF_MICROWIRE             (0x20)

#define DW_SPI_CTRLR0_SLV_OE_DISABLE            (1 << 10)
#define DW_SPI_CTRLR0_SLV_OE_ENABLE             (0)

/**
 * DesignWare SPI hal Interrupt Status Flags
 */
#define DW_SPI_TX_OVERFLOW_ERROR                (0x2)
#define DW_SPI_RX_UNDERFLOW_ERROR               (0x4)
#define DW_SPI_RX_OVERFLOW_ERROR                (0x8)

#define DW_SPI_ISR_RX_FIFO_INT_MASK             (0x10)
#define DW_SPI_ISR_TX_FIFO_INT_MASK             (0x1)
#define DW_SPI_ISR_TX_OVERFLOW_INT_MASK         (0x2)
#define DW_SPI_ISR_RX_UNDERFLOW_INT_MASK        (0x4)
#define DW_SPI_ISR_RX_OVERFLOW_INT_MASK         (0x8)

/**
 * DesignWare SPI hal Status Flags
 */
#define DW_SPI_SR_DCOL                          (0x40)
#define DW_SPI_SR_TXE                           (0x20)
#define DW_SPI_SR_RFF                           (0x10)
#define DW_SPI_SR_RFNE                          (0x8)
#define DW_SPI_SR_TFE                           (0x4)
#define DW_SPI_SR_TFNF                          (0x2)
#define DW_SPI_SR_BUSY                          (0x1)

/**
 * DesignWare SPI hal ssi enable macros
 */
/* Macros */
#define DW_SPI_SSI_ENABLE                       (1)     /*!< SSI Enable */
#define DW_SPI_SSI_DISABLE                      (0)     /*!< SSI Disable */

/**
 * DesignWare SPI hal interrupt mask macros
 */
#define DW_SPI_IMR_MSTIM                        (0x20)  /*!< Multi-Master Contention Interrupt Mask */
#define DW_SPI_IMR_RXFIM                        (0x10)  /*!< Receive FIFO Full Interrupt Mask */
#define DW_SPI_IMR_RXOIM                        (0x08)  /*!< Receive FIFO Overflow Interrupt Mask */
#define DW_SPI_IMR_RXUIM                        (0x04)  /*!< Receive FIFO Underflow Interrupt Mask */
#define DW_SPI_IMR_TXOIM                        (0x02)  /*!< Transmit FIFO Overflow Interrupt Mask */
#define DW_SPI_IMR_TXEIM                        (0x01)  /*!< Transmit FIFO Empty Interrupt Mask */

#define DW_SPI_IMR_XFER                         (DW_SPI_IMR_TXEIM | DW_SPI_IMR_RXFIM | DW_SPI_IMR_TXOIM | DW_SPI_IMR_RXOIM | DW_SPI_IMR_RXUIM)

#define DW_SPI_SSI_IDLE                         (1)
#define DW_SPI_SPI_TRANSMIT                     (1)
#define DW_SPI_SPI_RECEIVE                      (2)
#define DW_SPI_SSI_MASTER                       (1)
#define DW_SPI_SSI_SLAVE                        (0)

#endif /* __DW_SPI_HAL_H__ */
